1. Field of the Invention
The invention relates to a digital control loop and a method for generating clock signals with a high phase stability.
2. Description of the Related Art
To generate clock signals in integrated circuits, a multiplicity of clock signals having different phase angles relative to one another is often needed. Analog or digital control loops are used for phase generation and phase control in fast serial data transmission.
FIG. 4A shows a conventional digital control loop which achieves phase generation, i.e. the generation of clock signals with different phase angles with respect to one another, by using a digitally controlled delay line DL. The control loop consists of a phase detector PD, a digital loop filter DLF and the digitally controlled delay line DL. Starting with a reference clock signal Sref having a phase Φref, the delay line DL generates by means of propagation time delay a new clock signal Sout which usually consists of a number of individual phase signals which are provided via individual electrical lines and have different phase shifts relative to the reference clock signal Sref. The individual phase signals, in turn, are oscillation signals which are output as phase-shifted clock signals. Typical phase shifts for the individual clock signals with respect to the reference phase Φref are 45°, 90°, 135° and 180°.
To keep the relative phase angle of the generated clock signal Sout or of the individual phase signals, respectively, constant, the control loop has a feedback path. In this arrangement, a part of the clock signal Sout, as feedback signal Sfb is compared with the reference clock signal Sref by means of the phase detector PD. The feedback signal Sfb used is often the 180° phase signal of the clock signal Sout generated. Depending on the relative phase angle between the reference clock signal Sref and the generated clock signal Sout, the phase detector PD outputs a digital correction signal X. This, in most cases binary, correction signal X is transferred to the digital loop filter DLF which generates a digital control signal Y. The control signal Y is several bits wide in most cases and it is also called control word Y. The control word Y is transferred to the delay line DL and controls the delay time effected in the digital delay line DL. The result of this postregulation of the delay time is that the phase angle remains constant over a long period.
For the local phase generation, the digital control signal Y generated by the control loop can now be used several times. As shown in FIG. 4B, the control signal, together with the reference clock signal Rref, is transferred to a number of slave delay lines SDL distributed over a chip. These then generate the phases needed locally. This makes it possible to dispense with a more elaborate distribution of all phase signals over large distances which would entail considerable matching problems. Instead, only the reference clock signal Sref and the control signal Y need to be distributed over relatively large distances. The phase angle is regulated via the master delay-locked loop (Master DLL).
To regulate the phase angle, the phase detector PD usually generates a binary correction signal X, i.e. it generates an early/late information item in the form of digital pulses in dependence on the relative phase angle of the feedback signal in comparison with the reference clock signal. Due to the principle involved, such a phase detector PD combined with an integrating loop filter requires in the case of a constant reference phase Φref an oscillation of the feedback phase Φfb in the steady state so that the number of “early” and “late” information items of the correction signal X remains constant in the temporal mean. The associated oscillation of the correction signal X, in turn, leads to an oscillation of the control word Y between two values and thus, in turn, to oscillations of the output phases or of the phase signals generated, respectively. This corresponds to an inherent noise of the control loop.
FIG. 4C shows a conventional control loop which comprises a phase interpolator PI as a further possibility for generating clock signals with certain or determinable phase angles. This phase interpolator is supplied with a first phase reference signal Si and a second phase reference signal Sq. Depending on the control signal Y received, the phase interpolator PI outputs a clock signal Sout, the phase Φout of which is between the phase Φi of the first phase reference signal Si and the phase Φq of the second phase reference signal Sq. The exact relative phase angle is controlled or determined by the control word Y. The control signal Y is generated analogously to the examples shown previously.
Using phase interpolators makes it possible to achieve even finer gradings in the relative phase angle.
As a result, however, fluctuations or oscillations in the relative phase angle have even more severe effects on the ability to distinguish the individual clock signals. Particularly when a number of control loops are connected in cascade in order to achieve, for example, firstly a coarse grading of the phases by means of delay lines and, on the basis of the clock signals obtained during this process, a finer grading of the phase angle by means of phase interpolators, oscillations can accumulate in the phase of the clock signals. As a result, the fineness of the grading for still distinguishable phase angles is restricted to a minimum grading which must be greater than the amplitude of the oscillations of the phase angles.